Physically-addressable solid state disk (ssd) and a method of addressing the same

ABSTRACT

A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD) and is addressable using physical addresses associated with user data that are provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of the user data in the physically-addressed SSD. The flash tables are maintained in the non-volatile memory modules.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/542,516, filed on Nov. 14, 2014, by Siamack Nemazie and entitled “AComputer System With Physically-Addressable Solid State Disk (SSD) and AMethod of Addressing the Same”, which is a continuation of U.S. patentapplication Ser. No. 13/769,710, filed on Feb. 18, 2013, by SiamackNemazie and entitled “Storage System Employing MRAM and PhysicallyAddressed Solid State Disk”, which is a continuation-in-part of U.S.patent application Ser. No. 13/745,686, filed on Jan. 18, 2013, bySiamack Nemazie and entitled “Physically Addressed Solid State DiskEmploying MRAM”, which is a continuation-in-part of U.S. patentapplication Ser. No. 13/673,866, filed on Nov. 9, 2012, by SiamackNemazie and entitled “SYSTEM EMPLOYING MARAM AND PHYSICALLY ADDRESSEDSOLID STATE DISK”, which is a continuation-in-part of U.S. patentapplication Ser. No. 13/570,202, filed on Aug. 8, 2012, by SiamackNemazie and Ngon Van Le, and entitled “SOLID STATE DISK EMPLOYING FLASHAND MAGNETIC RANDOM ACCESS MEMORY (MRAM)”, which claims priority U.S.Provisional Application No. 61/538,697, filed on Sep. 23, 2011, entitled“Solid State Disk Employing Flash and MRAM”, by Siamack Nemazie,incorporated herein by reference as though set forth in full.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to storage systems, and particularly tostorage systems utilizing physically-addressed solid state disk (SSD).

2. Background

Solid State Drives (SSDs) using flash memories have become a viablealternative to Hard Disc Drives (HDDs) in many applications. Suchapplications include storage for notebook, tablets, servers andnetwork-attached storage appliances. In notebook and tabletapplications, storage capacity is not too high, and power and or weightand form factor are key metric. In server applications, power andperformance (sustained read/write, random read/write) are key metrics.In network-attached storage appliances, capacity, power, and performanceare key metrics with large capacity being achieved by employing a numberof SSDs in the appliance. SSD may be directly attached to the system viaa bus such as SATA, SAS or PCIe.

Flash memory is a block-based non-volatile memory with each blockorganized into and made of various pages. After a block is programmedinto the flash memory, it must be erased prior to being programmedagain. Most flash memory require sequential programming of pages withina block. Another limitation of flash memory is that blocks can only beerased for a limited number of times, thus, frequent erase operationsreduce the life time of the flash memory. A Flash memory does not allowin-place updates. That is, it cannot overwrite existing data with newdata. The new data are written to erased areas (out-of-place updates),and the old data are invalidated for reclamation in the future. Thisout-of-place update causes the coexistence of invalid (i.e. outdated)and valid data in the same block.

Garbage Collection is the process to reclaim the space occupied by theinvalid data, by moving valid data to a new block and erasing the oldblock. But garbage collection results in significant performanceoverhead as well as unpredictable operational latency. As mentioned,flash memory blocks can be erased for a limited number of times. Wearleveling is the process to improve flash memory lifetime by evenlydistributing erases over the entire flash memory (within a band).

The management of blocks within flash-based memory systems, includingSSDs, is referred to as flash block management and includes: Logical toPhysical Mapping; Defect management for managing defective blocks(blocks that were identified to be defective at manufacturing and growndefective blocks thereafter); Wear leveling to keep program/erase cycleof blocks within a band; Keeping track of free available blocks; andGarbage collection for collecting valid pages from a plurality of blocks(with a mix of valid and invalid page) into one block and in the processcreating free blocks. The flash block management requires maintainingvarious tables referred to as flash block management tables (or “flashtables”). These tables are generally proportional to the capacity ofSSD.

Generally, the flash block management tables can be constructed frommetadata maintained on flash pages. Metadata is non-user informationwritten on a page. Such reconstruction is time consuming and generallyperformed very infrequently upon recovery during power-up from a failure(such as power fail). In one prior art technique, the flash blockmanagement tables are maintained in a volatile memory, and as mentioned,the flash block management tables is constructed from metadatamaintained in flash pages during power-up. In another prior arttechnique, the flash block management tables are maintained in abattery-backed volatile memory, utilized to maintain the contents ofvolatile memory for an extended period of time until power is back andtables can be saved in flash memory. In yet another prior art technique,the flash block management tables are maintained in a volatile RAM, theflash block management tables are periodically and/or based on someevents (such as a Sleep Command) saved (copied) back to flash, and toavoid the time consuming reconstruction upon power-up from a powerfailure additionally a power back-up means provides enough power to savethe flash block management tables in the flash in the event of a powerfailure. Such power back-up may comprise of a battery, a rechargeablebattery, or a dynamically charged super capacitor.

The flash block management is generally performed in the SSD and thetables reside in the SSD. Alternatively, the flash block management maybe performed in the system by a software or hardware, commandsadditionally include commands for flash management commands and thecommands use physical addresses rather than logical addresses. An SSDwith commands using physical addresses is referred to asPhysically-Addressed SSD. The flash block management tables aremaintained in the (volatile) system memory.

A storage system (also referred to as “storage array”, or “storageappliance”) is a special purpose computer system attached to a network,dedicated to data storage and management. The storage system may beconnected to Internet Protocol (IP) Network running Network File System(NFS) protocol or Common Internet File System (CIFS) protocol orInternet Small Computer System (iSCSI) protocol or to a Storage AreaNetwork (SAN) such as Fiber Channel (FC) or Serial Attached SCSI (SAS)for block storage.

In a storage system employing physically-addressed SSD which maintainsthe flash block management tables on the system memory that has no powerback-up means for the system and no power back-up means for the systemmemory, the flash block management tables that reside in the systemmemory are lost and if copies are maintained in the flash onboard theSSD, the copies may not be updated and/or may be corrupted if powerfailure occurs during the time a table is being saved (or updated) inthe flash memory.

Hence, during a subsequent power up, during initialization, the tableshave to be inspected for corruption due to power fail and, if necessary,recovered. The recovery requires reconstruction of the tables to becompleted by reading metadata from flash pages and results in furtherincrease in delay for system to complete initialization. The process ofcomplete reconstruction of all tables is time consuming, as it requiresmetadata on all pages of SSD to be read and processed to reconstruct thetables. Metadata is non-user information written on a page. This flashblock management table recovery, during power-up, further delays thesystem initialization, the time to initialize the system is a key metricin many applications.

Yet another similar problem of data corruption and power fail recoveryarises in SSDs and also HDDs when write data for write commands (orqueued write commands when command queuing is supported) is cached in avolatile system memory and command completion issued prior to writing tomedia (flash or Hard Disc Drive). It is well known in the art thatcaching write data for write commands (or queued write commands whencommand queuing is supported) and issuing command completion prior towriting to media significantly improves performance.

Additionally, file systems and storage systems employ journaling orlogging for error recovery, the journal or log associated with a commandor commands is saved in a persistent storage. In the event of a powerfail or system crash or failure the journal or log is played back torestore the system to a known state.

As mentioned before, in some prior art techniques, a battery-backedvolatile memory is utilized to maintain the contents of volatile memoryfor an extended period of time until power is back and tables can besaved in flash memory.

Battery backup solutions for saving system management data or cacheduser data during unplanned shutdowns are long-established but havecertain disadvantage including up-front costs, replacement costs,service calls, disposal costs, system space limitations, reliability and“green” content requirements.

What is needed is a system employing physically-addressed SSD toreliably and efficiently preserve flash block management tables in theevent of a power interruption.

SUMMARY OF THE INVENTION

Briefly, in accordance with one embodiment of the invention, a storagesystem includes a Central Processing Unit (CPU) that has aphysically-addressed solid state disk (SSD) and is addressable usingphysical addresses associated with user data that are provided by ahost. The user data is to be stored in or retrieved from thephysically-addressed SSD in blocks. Further, a non-volatile memorymodule is coupled to the CPU and includes flash tables used to manageblocks in the physically addressed SSD. The flash tables have tablesthat are used to map logical to physical blocks for identifying thelocation of the user data in the physically-addressed SSD. The flashtables are maintained in the non-volatile memory modules.

Further, a non-volatile memory module is coupled to the CPU and used forstoring flash block management tables (also referred to herein as “flashtables”), caching data, and maintaining a journal (the terms “journal”and “log” are used interchangeably herein), in addition to flash tablesused to manage blocks in the physically-addressed SSD. The flash tableshave tables that are used to map logical to physical blocks foridentifying the location of stored data in the physically-addressed SSD.The flash tables are maintained in the non-volatile memory modulesthereby avoiding reconstruction of the flash tables upon powerinterruption.

These and other features of the invention will no doubt become apparentto those skilled in the art after having read the following detaileddescription of the various embodiments illustrated in the severalfigures of the drawing.

IN THE DRAWINGS

FIG. 1 shows a storage system 700, in accordance with an embodiment ofthe invention.

FIG. 1 a shows exemplary contents of the system memory 762, the NVmodule 762, and the flash subsystem 110, in accordance with anembodiment of the invention.

FIG. 1 b shows exemplary contents of the system memory 746, the NVmodule 762, and the flash subsystem 110, in accordance with anotherembodiment of the invention.

FIG. 2 shows a storage system 810, in accordance with another embodimentof the invention.

FIG. 3 shows a storage system 866, in accordance with another embodimentof the invention.

DETAILED DESCRIPTION OF THE VARIOUS EMBODIMENTS

In an embodiment of the invention, a storage system includes a CentralProcessing Unit (CPU) a system memory, a network interface controllerfor connection to a network and one or more physically addressed SSD(paSSD), coupled to the CPU through a system bus such as PeripheralComponent Interconnect Express (PCIe) bus and addressable using physicaladdresses for storing data provided via the network. The data is to bestored in or retrieved from the physically-addressed SSD in blocks.

Further, a non-volatile memory module is coupled to the CPU and used forstoring flash block management tables (also referred to herein as “flashtables”), caching data, and maintaining a journal. The flash tables havetables that are used to map logical to physical blocks for identifyingthe location of stored data in the physically addressed SSD. The flashtables are maintained in the non-volatile memory modules therebyavoiding reconstruction of the flash tables upon power interruption.

In one embodiment, all flash block management tables are in one or morenon-volatile memory module comprised of MRAM coupled to processor thoughmemory channels.

In an alternate embodiment, tables are maintained in system memory andare near periodically saved in flash onboard the physically-addressedSSD and the parts of the tables that are updated since last saved areadditionally maintained in a non-volatile memory module comprised ofMRAM that is coupled to the processor though memory channels, thecurrent version of the block management table that is in flash alongwith the updates that are saved in MRAM being used to reconstruct theflash block management tables in system memory upon system power-up.

In yet another alternate embodiment, in order to reduce the size ofupdates in MRAM and frequency of flash table copy back to flash, one ormore of the updates (along with revision numbers), are also copied toflash. The current version of the block management table that is savedin flash, along with past updates, that are saved in flash and recentupdates that are saved in MRAM are used to reconstruct the flash blockmanagement tables in system memory upon system power-up.

In yet another embodiment, the contents of MRAM are coupled to theprocessor through a system bus such as Serial Peripheral Interface (SPI)bus or PCIe with analogous methods of the invention used to reconstructthe flash block management tables in system memory upon system power-up,such as by either using the current version of the block managementtable in flash along with recent updates that are saved in MRAM or usingthe current version of the block management table in flash along withthe past updates that are saved in flash. The recent updates that aresaved in the MRAM are used to reconstruct the flash block managementtables in the system memory upon power-up.

In yet another embodiment, the physically-addressable SSD includes aflash subsystem and a non-volatile memory comprised of MRAM. In someembodiment of the invention, flash block management tables aremaintained in the system memory and are nearly periodically saved in theflash subsystem onboard the paSSD and the parts of the tables that areupdated since the last save are additionally maintained in the MRAM thatis onboard the paSSD via methods that physically address the MRAM ratherthan the flash.

In all the above embodiments, cached data and/or journals can optionallybe stored in the MRAM.

Referring now to FIG. 1, a storage system 800 is shown, in accordancewith an embodiment of the invention. The system 800 is shown to includea Central Processor Unit (CPU) 710 (also known herein as “processor710”), a system memory 746, a non-volatile (NV) memory module 762, abasic input and output system (BIOS) 740, and a bank ofphysically-addressed solid state disks (SSD) 750-1 to 750-p, ‘p’ beingan integer value, in accordance with an embodiment of the invention. A“bank”, as used herein, refers to one or more.

The CPU 710 of system 800 is shown to include a bank of CPU cores 712-1through 712-n, ‘n’ being an integer value, a bank of memory controllers724-1 through 724-m, ‘m’ being an integer value, shown coupled to a bankof memory channels 726-1 through 726-m, a PCIe controller 730. The CPU710 is further shown to include an NV module controller 760, and a SPIcontroller 732. The network interface controller 802 is shown coupledthrough a PCIe bus 804 to PCIe controller 730 and CPU 710.

The bank of paSSDs 750-1 to 750-p is shown coupled to the CPU 710through a respective one of a bank of sockets 737-1 to 737-p. The NVmodule 762 is shown coupled to the CPU 710 through a NV memory channel764. The system memory 746 is shown coupled to include a bank ofvolatile RAM (DRAM) modules 747-1 through 747-m that are coupled to thememory controllers 724-1 through 724-m through a respective one of abank of memory channels 726-1 to 726-m.

The PCIe controller 730 is shown coupled to a bank of PCIe busses 731-1through 731-p that couple the CPU 710 to a bank of paSSD 750-1 through750-p, Further shown in FIG. 1 is the CPU 710 including a (SPI)controller 732, which is shown coupled to the BIOS 740, the BIOS 740shown residing externally to the CPU 710.

The NV module 762, which is also shown to reside externally to the CU710, includes a bank of MRAMs 763-1 through 763-k that are shown coupledto the NV module controller 760 via the NV memory channel 764. In anembodiment of the invention, the NV memory channel 764 is analogous tothe memory channels 726/728 and the NV module controller 760 isanalogous to the memory controller 724.

The NV memory channel 764 couples the NV module 762 to the NV modulecontroller 760 of the CPU 710. In an embodiment of the invention, the NVmemory channel 764 is a DRAM memory channel.

In some embodiments, in addition to using the NV memory module 762 asflash tables, the NV memory module 762 is used by the system 800 asnon-volatile cache for storing in-coming data (data that is input to thesystem 800) and or storing a journal.

Although a memory module is employed in the embodiments wherein one ormemory devices are on a removable unit, other embodiments of employingmemory devices in the system such as non-removable memory devices allwithin the scope of invention.

Network Interface Controller 802 is shown coupled to the processor 710via the PCIe bus 804 and coupled to network interface 806 for connectionto a network via network interface 806. The network interface controller802 implements the circuitry required to communicate with a specificphysical layer and the data link layer for receiving and transmittinginformation packets including command/status and data. The networkinterface controller 802 implements the circuitry required for upperlayer protocols (the layer above the data link layer, such as transportlayer, application layer, and the like).

In some embodiments, the network interface 806 is a Gigabit or tenGigabit Ethernet running Internet Small Computer System Interface(iSCSI) and in other embodiments, it is a Serial Attached SCSI (SAS) orFiber Channel (FC), which are generally used with block storageprotocols. In yet other embodiments, the network interface 806 isGigabit or ten Gigabit Ethernet running network file storage (NFS)protocol. All of the foregoing interfaces are known in the art. Inparticular, the Ethernet capabilities are either integrated into the CPUor implemented via a low-cost dedicated NIC 802, connected through thePCIe bus 804 as shown in FIG. 1.

In some embodiments, the flash subsystem 110 is made of flash NANDmemory. In some embodiment, the flash subsystem 110 is made of flash NORmemory.

The CPU 710 of storage system 800 is shown to include one or morephysically-addressed solid state disk 750-1 through 750-p, wherein theblocks are addressed with a physical rather than a logical address. ThepaSSD 750 includes flash subsystem 110. For example, thephysically-addressed solid state disk 750-1 is shown to include theflash subsystem 110-1. In the storage system 800 of FIG. 1, flash blockmanagement is performed by a software driver (also known herein as the“driver”) 702 that is loaded during initialization of the system 800,after power-up. In addition to user commands, commands sent to the paSSD750 include commands for flash management (including garbage collection,wear leveling, saving flash tables) and these commands use physicaladdress rather than logical address.

In one embodiment of the invention, as shown in FIG. 1 a, the flashtable 201 is saved in the non-volatile memory module 762 that is made ofthe MRAMs 763-1 thru 763-k of the embodiment of FIG. 1.

FIG. 1 a shows exemplary contents of the system memory 746, the NVmodule 762, and the flash subsystem 110, in accordance with anembodiment of the invention. The system memory 746 is shown to include adriver 702, the NV module 762 is shown to include the flash tables 201,journal 251, cache 261, and the flash subsystem 110 is shown to includethe user data 366. The driver 702, shown saved in system memory 746, inFIG. 1 a, performs flash block management. The flash tables 201 aretables generally used for management of the flash memory blocks withinthe paSSD 750 of FIG. 1 and the user data 366 is generally informationreceived by the paSSD 750 from the CPU 710 to be saved. The flash tables201 include tables used for managing flash memory blocks. The driver 702generally manages the flash memory blocks. As shown in FIG. 1 a, theflash table 201 is maintained in the module 762.

As noted above, the flash subsystem 110 is addressed using physical andnot logical addresses, provided by the CPU 710.

In an alternate embodiment, the flash tables 201 are maintained in thesystem memory 762 and are substantially periodically saved in the flashsubsystem 110 of the paSSD 750, and the parts of the tables 201 that areupdated (modified) since the previous save are additionally saved in thenon-volatile memory module 762.

FIG. 1 b shows exemplary contents of the system memory 746, the NVmodule 762, and the flash subsystem 110, in accordance with anotherembodiment of the invention. In FIG. 1 b, the system memory 746 is shownto include the driver 702 in addition to the flash tables 201. The NVmodule 762 is shown to include the table updates 302, journal 251, cache261 and the flash subsystem 110 is shown to include table copies 360 andthe user data 366. As previously noted, the flash tables 201 are tablesthat are generally used for management of blocks within the SSD 750. Thetable updates 302 are generally updates to the flash tables 201 sincethe last copy of the flash tables 201 was initiated until a subsequentcopy is initiated. The table copies 360 are snapshots of the flashtables 201 that are saved in the flash subsystem 110. This is furtherexplained in U.S. patent application Ser. No. 13/673,866, filed on Nov.9, 2012, by Siamack Nemazie, and entitled “System Employing MRAM andPhysically Addressed Solid State Disk”, the contents of which areincorporated herein by reference as though set forth in full. The userdata 366 is information provided by the host (CPU 710 of FIG. 1).

In some embodiments, the NV module 762 includes spin torque transferMRAM (STTMRAM).

In some embodiments, the NV module 762 is coupled to the CPU 710 via asystem bus. An exemplary system bus is Serial Protocol Interconnect(SPI) or PCIe.

Accordingly, storage system 800 and the flash tables 201 are used tomanage blocks in the paSSD 750. The flash tables 201 include tables thatare used to map logical blocks to physical blocks for identifying thelocation of stored data in the paSSD 750 and the flash tables aremaintained in the NV module 762, which advantageously avoidsreconstruction of the flash tables upon power interruption of thestorage system 800.

Additionally, a cache or in particular a write back cache is maintainedin the non-volatile memory module 762. The write cache contents arewritten to the paSSD 750 upon triggers, such trigger including, amongothers, the cached data in the cache 261 to reach a certain limit. Inone embodiment, the contents of the cache 261 are written to the psSSDsin units of pages that are each aligned to a page boundary. In oneembodiment, partial pages are maintained in the non-volatile memorymodule 762 and coalesced with other writes to write a full page to SSDs.In another embodiment, the partial page in the non-volatile memorymodule 762 is merged with the unmodified portion of the page in SSD, sothat the page in the cache reflects the state of the page.

Journaling is generally a known practice for logging the changes thatwill be made in a journal (usually a circular log in a dedicated area)before committing them to the main storage. In the event of a systemcrash or power failure, such file systems are quicker to bring backonline and less likely to become corrupted. A “journal” maybe optionallymaintained in the non-volatile memory module 762. In the exemplaryembodiments the NV module 762 is shown to include a journal 251

FIG. 2 shows a storage system 810, in accordance with another embodimentof the invention. The system 810 is analogous to the system 800 exceptthat the system 810 additionally includes a PCIe-to-Flash bus Bridgecontroller 735 to couple a plurality of PCIe buses 731-1 through 731- toa bank of flash buses 733-I (where i is from 1 through q) each coupledto a paSSD 750-i through connector 737-I, ‘i’ being an integer value. Anexample of a flash bus is Open NAND Flash Interface (ONFI).

Except for a different interface to the paSSDs, the operation of system810 is analogous to system 800.

FIG. 3 shows a storage system 865, in accordance with another embodimentof the invention. The system 865 is analogous to the system 800 exceptthat the system 865 does not employ an NV module, and the paSSDs 850-1through 850-p employ MRAM specifically MRAMs 140/150-1 through 140/150-prespectively. The operation of paSSDs 850-1 through 850-p and itsoperation in a system is further explained in U.S. patent applicationSer. No. 13/745,686, filed on Jan. 18, 2013, by Siamack Nemazie, andentitled “Physically Addressed Solid State Disk Employing MRAM”, thecontents of which are incorporated herein by reference as though setforth in full.

Except for a removing NV module 762 and employing a paSSD employing MRAMthe structure of system 865 is analogous to system 800.

Although the invention has been described in terms of specificembodiments, it is anticipated that alterations and modificationsthereof will no doubt become apparent to those skilled in the art. It istherefore intended that the following claims be interpreted as coveringall such alterations and modification as fall within the true spirit andscope of the invention.

What is claimed is:
 1. A storage system comprising: a Central ProcessingUnit (CPU): at least one physically-addressed solid state disk (SSD)that is addressable using physical addresses associated with user data,the at least one physically-addressed SSD being provided by a host, theuser data to be stored in or retrieved from the at least onephysically-addressed SSD in blocks; a non-volatile memory module coupledto the CPU and configured to store changes to tables, the tables used tomap logical to physical block addresses for identifying the location ofstored data in the at least one physically-addressed SSD, wherein thetables are moved to the at least one physically-addressed SSDs and thechanges to the tables are maintained in the non-volatile memory module;and a network interface controller coupled through a bus to the CPU. 2.The storage system of claim 1, wherein upon the non-volatile memorymodule having associated therewith an available capacity and upon theavailable capacity reaching a desired available capacity, the tablesbeing moved to the memory.
 3. The storage system, as recited in claim 1,wherein the at least one physically-addressed solid state disk (SSD)includes a subsystem and the subsystem being made of flash NAND memory.4. The storage system, as recited in claim 1, further including a bankof memory controllers coupled to a bank of volatile RAM modules througha respective one of a bank of memory channels.
 5. The storage system, asrecited in claim 1, wherein the at least one physically-addressable SSDincludes a subsystem.
 6. The storage system, as recited in claim 5,wherein the subsystem is made of flash NAND memory.
 7. The storagesystem, as recited in claim 1, wherein the at least onephysically-addressed SSD is coupled through another bus to the CPU. 8.The storage system, as recited in claim 7, wherein the bus and theanother bus are the same bus.
 9. The storage system, as recited in claim7, wherein the bus and the another bus are different busses.
 10. Thestorage system, as recited in claim 7, wherein the bus is a PCIe bus.11. The storage system, as recited in claim 7, wherein the another busis a PCIe bus.
 12. The storage system, as recited in claim 7, furtherincluding a bridge controller configured to couple the bus and theanother bus.
 13. The storage system, as recited in claim 7, wherein thebus and the another bus are PCIe busses.
 14. The storage system, asrecited in claim 1, wherein the non-volatile memory module includesmagnetic random access memory (MRAM).
 15. The storage system, as recitedin claim 1, wherein the non-volatile memory module includes spintransfer torque magnetic random access memory (STTMRAM).
 16. The storagesystem, as recited in claim 1, wherein the non-volatile memory module iscoupled to the CPU through a memory channel.
 17. The storage system, asrecited in claim 16, wherein the non-volatile memory module is coupledto a CPU through a dynamic random access memory (DRAM) memory channel.18. The storage system, as recited in claim 1, wherein the non-volatilememory module is coupled to the CPU via a system bus.
 19. The storagesystem, as recited in claim 1, further including a system memoryconfigured to store a software driver configured to manage the flashtables.
 20. The storage system, as recited in claim 1, wherein thenon-volatile memory module includes a cache configured to store the userdata.
 21. The storage system, as recited in claim 1, wherein thenon-volatile memory module is configured to store a journal and thejournal is configured to log the changes before the changes are made tothe non-volatile memory module.
 22. The storage system, as recited inclaim 1, further including another bus coupling the at least onephysically-addressed SSD to the CPU.
 23. The storage system, as recitedin claim 22, wherein the another bus is a PCIe bus.
 24. The storagesystem, as recited in claim 23, wherein the CPU includes a controller.25. The storage system, as recited in claim 24, wherein the controlleris coupled to the another bus.
 26. The storage system, as recited inclaim 1, wherein the CPU comprises a plurality of CPU cores.
 27. Thestorage system, as recited in claim 1, further including a bridgecontroller configured to couple the at least one physically-addressedSSD to the CPU.